Correction of long term drift and short term fluctuating corruption of a signal

ABSTRACT

An arrangement to remove drift and wow and flutter in a tape recording comprising recording a control signal tone derived from a reference clock (159) in a dedicated control channel or embedded in a signal channel. The control signal on playback (151) is compared to the reference signal in an up/down counter (172) and the difference is used to correct the speed of the tape drive. The drift corrected control tone signal is connected through a programmable RAM delay (154) and a latch (179) to a D/A converter (156). The delayed analogue control signal and the reference signal are limited then connected to phase comparator counter (158) which is triggered by the leading edge of the reference signal and read by the leading edge of the squared control signal to measure the time delay between them as a number of RAM (154) samples (N) and subsamples (n). The measured time delay is used to advance or retard the Read address (155) relative to the Write address in the RAM delay (154) where unit change in the tap address (N) is equal to 20 usec in the example. The remaining time delay (0-19) usec is connected to a phase delay circuit (178) effective to delay readout from the RAM via the latch (179) in one microsecond intervals in the example.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to signal processing and in particular, though notexclusively, to the correction of drift and wow and flutter in signalsthat have been recorded.

2. Discussion of Prior Art

When a signal is transmitted through a medium, there may be fluctuatingand drift time delays imposed on the signal due to changes in thepropagating medium. Such a medium may have an analogue in a taperecording system where a signal is subjected to delays during recordingand playback.

When making recordings of signals it is impossible to maintain aperfectly constant tape speed because of limitations imposed bymechanical and environmental conditions. There will therefore be shortterm variations (wow and flutter) and also long term variations (drift)in the recorded, and subsequently, played back signals. The short termvariations appear as a recognisable frequency modulation on the recordedsignals. The maximum deviation of this change in frequency will dependupon the mechanical precision of the recording system as will thefrequency of modulation (rate of variation). Variation frequencies up to10 Hz are normally referred to as `wow` whilst those above 10 Hz arecalled `flutter`. Very slow variations and steady state errors (longterm average speed errors) are called `drift`. These speed induced drifterrors are responsible for creating timing inaccuracies during playbackand from recording to recording etc. Drift is likewise caused by thelimited precision of the mechanical drive but it is also dependent uponthe elasticity properties of the tape, tape tensions, the surfaceproperties of the tape, the ambient temperature, air humidity and uponany variations in mains supply.

Wow, flutter and drift performances can often be held within acceptablelimits without resorting to sophisticated systems since the human ear isunable to detect some short term frequency variations (wow and flutter)with the same level of perception over the entire audio frequency range.Thus it is possible to minimise the apparent wow and flutter by ensuringthat the predominant frequency of variation is not close to 4 Hz, thefrequency of maximum perception.

When used for recording and playback of data, however, modern electronicsystems can be susceptible to very small frequency, phase and timediscrepancies. Thus, when recordings are made of particular `timesynchronous` and phase modulated signals, these signals will becorrupted by the relatively very much larger phase distortions producedby the wow and flutter, and the drift will cause time slip and frequencyshifting in the playback signal.

SUMMARY OF THE INVENTION

The object of the invention is to provide means to reduce or overcomeshort-term and drift time delays experienced by a signal transmitted viaa medium such as a recording medium.

The invention provides in one form a signal correction system for arecording system comprising a means to transmit for recording a signaland a control reference tone and playback receiving means to receive thesignal and the reference tone, wherein the receiving means includes alocal oscillator means to produce an identical tone to the transmittedcontrol reference tone and comparator means to compare the frequency ofthe control tone with the local oscillator tone; characterised in that:the receiving means further includes:

a) drift correction means connected to the frequency comparator means toapply a common frequency shift to the received signal and the referencetone to reduce to zero the difference output from the frequencycomparator; the frequency conparator including means to continuouslycount the cycles of the received reference and the local oscillatortones such that differences between the running counts of the two tonesare repetitively used for drift correction;

b) a phase comparator circuit to compare the phase of thedrift-corrected reference tone with the phase of the local oscillatortone; and

c) short term flutuation correction means connected to the phasecomparator circuit to apply to the received signal and thedrift-corrected reference tone a common phase delay to reduce to zerothe difference output from the phase comparator.

In an alternative form the invention provides a signal correction systemcomprising a transmission means to transmit a signal and a controlreference tone and receiving means to receive the signal and thereference tone, wherein the receiving means includes a local oscillatormeans to produce an identical tone to the transmitted control referencetone and comparator means to compare the frequency of the control tonewith the local oscillator tone; characterised in that; the receivingmeans further includes:

a) correction means connected to the frequency comparator means to applya common frequency shift to the received signal and the reference toneto reduce to zero the difference output from the frequency comparator;the frequency conparator including means to continuously count thecycles of the received reference and the local oscillator tones suchthat differences between the running counts of the two tones arerepetitively used for correction;

b) a phase comparator circuit to compare the phase of thefrequency-corrected reference tone with the phase of the localoscillator tone; and

c) short term flutuation correction means connected to the phasecomparator circuit to apply to the received signal and thefrequency-corrected reference tone a common phase delay to reduce tozero the difference output from the phase comparator.

In one arrangement the frequency comparator means comprises a cyclicbinary counter having an output clocked by a signal derived from thelocal oscillator. Conveniently the cycling of the binary counter isdetermined by a detector connected to the counter and responsive to apredetermined binary number (N_(p)) to provide a reset signal to thecounter. Preferably the local oscillator-derived clock signal isproduced by connecting the local oscillator signal to the input of adivide-by-N_(p) /n, where n is an integer. Conveniently the output fromthe binary counter is clocked into an output latch circuit and the latchoutput is connected to a D/A converter to produce an analogue signalrepresentative of the frequency time/drift between the receivedreference tone and the local oscillator tone. Preferably the receivedreference tone is bandpass filtered and limited to minimise the effectsof fading and dropouts. The drift representative D/A output samples maybe connected to an active voltage integrator circuit comprising atransconductor and a capacitor.

Preferably the drift-corrected reference tone is connected via a fastprogrammable delay circuit to the phase comparator circuit and in theabove arrangements the short term fluctuation correction meanspreferably comprises the programmable delay circuit and a voltagecontrolled oscillator (VCO), the arrangement being such that the voltageoutput from the phase comparator is connected to the input of the VCOand the VCO output is connected to the delay circuit such that the phasecomparator error output is minimised.

Advantageously limiters are provided in the circuit connections to theinputs of the phase comparator. Preferably the output signal from theVCO is connected to a second delay circuit, identical to the first: thedraft corrected received signal being connected to the input to thesecond delay circuit and the drift and short term fluctuation correctedsignal being provided at the output thereof. Low pass filters may beprovided at the input and output of the second delay circuit. Each delaymay be a digital delay. More than one phase comparator stages of shortterm fluctuation correction may be provided.

In a particular arrangement 6 dB/octave low pass filter is connectedbetween the phase comparator and the VCO whereby the loop gain of thewow and flutter correction circuit decreases inversely in proportion tothe modulation frequency. This has been used to obtain inherentstability within the closed loop of an analogue circuit. A digitalimplimentation may incorporate more advanced techniques to allow ahigher gain and greater bandwidth to be useful.

In a particular arrangement of the invention for reduction of drift, wowand flutter in a tape recorder a single stable reference oscillator isprovided and arranged for connection to the tape recorder such that onrecord a control reference tone is connected to at least one taperecorder input with the frequency comparator and phase comparatorcircuits disabled and on playback the recorded signals to be corrected,together with the recorded reference tone, are connected to the signalcorrection system.

The reference signal may be provided as a reference embedded in eachinput channel of a multi-channel recorder or as a reference in adedicated reference channel.

When applied to a tape recorder, the drift correction means includes asignal connected from the output of the frequency comparator to the tapecapstan motor drive to vary the drive speed. In one example a lightdependent resistor may be used to correctly interface with the recorder.

In an alternative arrangement the frequency comparator means comprisesan up/down counter, the received control tone and the local referencetone being connected to respective count down and count up inputs andthe output difference signal being connected to a means effective toreduce the to zero the frequency difference between the control tone andthe reference tone.

The phase time delay for correcting the remaining phase differencesbetween the control and reference tone may advantageously be applied bya digital time delay circuit comprising in series a programmable RAMdelay and a RAM latch, and a phase adjuster for the latch, thearrangement being such that digital signal samples are clocked in to theWrite address of the RAM delay at frequency F and are read out from aprogrammable Read address to the latch to provide a time delay havingincremental value ΔT of 1/F, the clock signal to the RAM latch beingdelayed by a digitised time having an incremental value Δt in the range0 to 1/F, to thereby provide an overall time delay to an accuracy of Δt.

Advantageously the phase comparator comprises limiter means to squarethe control signal and the replica reference signal and a counterclocked by the reference signal and read by the squared control signal.Preferably the counter clock frequency is n times the RAM clockfrequency F and the phase comparator measures the phase difference inunits (N) of 1/F and (R) of 1/nF.

Conveniently there is provided means whereby the digitised phasedifference N+R, which may be positive or negative, is modified byconditional change of N such that R always represents a delayed phasedifference. Conveniently also, the Read address for the RAM is stored ina Read latch connected to an adder such that it can be adjusted by themodified N. R is then used to set the delay for the RAM latch.

BRIEF DISCUSSION OF THE DRAWINGS

The invention will now be described by way of example only withreference to the accompanying Drawings of which:

FIG. 1 shows a block diagram of an example of the invention applied tothe correction of a tape recorder drift, wow and flutter;

FIGS. 2a, 2b, 2c and 2d illustrate the signal formats for correction ofa single wideband channel and for dual 3 kHz channels;

FIG. 3 shows a block diagram of the FIG. 1 arrangement applied to a dual3 kHz channel recording system;

FIG. 4a is a block diagram of a standard frequency measurement circuit;

FIG. 4b shows a modification of FIG. 4a used for drift correction inFIGS. 1 and 3;

FIG. 5 is a block diagram of a drift compensation circuit adopting theFIG. 4b frequency counter;

FIG. 6 is a more detailed block diagram of the FIG. 5 circuit;

FIGS. 7 and 8 illustrate a block diagram and detector response for a wowand flutter circuit;

FIG. 9 is a block diagram of a wow and flutter correction circuitincorporating the FIG. 7 circuit;

FIG. 10 is a modified FIG. 9 circuit using cascaded feedback phasedetection circuits;

FIG. 11 is a graph showing the predicted wow and flutter reductionperformances for the FIG. 9 and 10 arrangements;

FIGS. 12 and 13 are block diagrams of digital delays for use in the wowand flutter correction circuits;

FIG. 14 is a schematic block diagram of an alternative form of theinvention;

FIG. 15 is a schematic representation of a digital circuit arrangementof the drift, wow and flutter correction circuit applied to a taperecorder;

FIG. 16 is a diagram to illustrate the operation of the FIG. 15 phasedifference measurement circuit; and

FIG. 17 is a more detailed version of FIG. 15 showing the tape recorderspeed control and the tape signal correction circuitry.

DETAILED DISCUSSION OF PREFERRED EMBODIMENTS

FIG. 1 shows a two-channel tape recorder 10 having L and R inputs 11,12,L and R outputs 13,14 and a tape drive speed control input 15. In thisarrangement an input signal to be recorded is connected to the R input12 and simultaneously a stable 5 kHz reference signal R_(s) from anoscillator 16 in a drift, wow and flutter correction circuit 17 isconnected to the L input 11. On playback, the recorded reference signalT_(c) and input signal S_(s) are connected to inputs 18,19 to thecorrection system 17. As will be described in greater detail, therecorded reference signal is compared (110) with the signal from theoutput 111 of the oscillator 16 to provide:

a) an output signal for connection to the speed control input 15 to thetape recorder to change the tape drive speed to correct the effect ofdrift in the output channels; and

b) a signal for correcting residual frequency fluctuations in the outputchannels.

The corrected output signal S'_(s) is then provided at the signal output112 of the correction circuit 17.

During a recording the correction circuit 17 is only used to provide thestable 5 kHz reference control tone R_(s) ; the tape speed drift controland the wow and flutter correction circuitry being disabled.

FIGS. 2a and 2b illustrate the spectra of recorded signals on the tracksof a 2-track tape recorder. On one track the 5 kHz control tone 20 isrecorded at a frequency positioned within the bandwidth of the recordedsignal S(F), 21. Also shown in FIG. 2b is the response 22 of a 5 kHzband pass filter which would generally be used at the playback output toimprove the signal to noise in the control tone channel.

The advantage of the FIGS. 2a and 2b arrangement using a dedicatedreference tone channel or track is that the input signal being recordedcan have a frequency response which overlaps the control tone frequency.On the other hand one track must be exclusively assigned for the controltone. A further disadvantage is that phase-shifting errors can existbetween any two (or more) recorded tracks. This problem occurs becausethe tape will `skew` as it passes over the record and playback heads.This is generally accepted as an insignificant factor during a recording(and playback) but it can now become the dominant limiting factor if acorrection system is employed (particularly if a cascaded technique isused to reduce wow and flutter to very small levels). This is becausethe system is unable to correct the phase skew errors produced betweenthe control tone track and the signal tracks. Unfortunately, theseinterchannel phase errors can be much greater than the residual errorsafter correction.

FIGS. 2c and 2d illustrate the frequency spectra in an alternative2-channel recording system with each channel having a signal bandwidthof 3 kHz. The right and left recorded signal spectra (FIGS. 2c and 2d,respectively) are indicated by reference numerals 23 and 24, and theseare filtered by 3 kHz low pass filters 25, 26 respectively beforeprocessing by a correction circuit. In this arrangement a control tone27, 28 of 5 kHz, i.e. above the upper frequency limit, is recorded oneach channel together with the two channel signals. Each channel canthen be processed separately to correct for drift, wow and flutter.

Ultimately, interchannel phase errors will depend on the quality of thetape recorder being used and their effect will depend upon the desiredwow and flutter figures to be achieved. If the required wow and flutterfigures cannot be achieved using a dedicated control tone channel it maybe necessary to use an embedded control tone in every recording channelas in FIG. 2b. Unfortunately, this can only be achieved with greaterelectronic complexity and provided (at all times) that the recordedsignal frequencies will be less than the control tone. The frequency ofthe control tone should ideally be as high as possible because higherfrequencies have a greater change in deviation frequency impressed uponthem due to drift, wow and flutter. This makes it much easier to detectthe highest rates of change (flutter) and reduces the risk ofinstability in the correction system because loop gains can beminimised. If the control tone can have a higher frequency than thesignals to be recorded then the detection circuits will operate with ahigher resolution than the signals it must correct because it will havehigher frequency deviations. This optimises the correction process.There may however be special exceptions to this if the signals to berecorded have gaps within their spectra which can be used to place thecontrol tone. Unfortunately it is not possible to use the maximumfrequency (that can normally be recorded as a signal) for the controltone because `drop out` and fading has a much greater effect at thesefrequencies. For this reason the control tone frequency will depend onthe performance of the tape recorder being used. Any complete drop outs,or deep fades, in the control tone signal will have a serious effect onthe operation of the correction system because it will produceinstantaneous phase and drift discontinuities. Fortunately it is howeverpossible to compensate for very short or rapid drop-outs and all but thedeepest fades by using electronic filtering. This will be describedlater.

A modified version of the FIG. 1 arrangement adapted for two channelrecording as illustrated in FIGS. 2a and 2b is shown in FIG. 3. Signalsto be recorded are connected to inputs 31, 32 of the correction circuit33 where they are first filtered by 3 kHz low band pass filters 34, 35and then mixed (36, 37) with the 5 kHz reference tone from theoscillator 16.

Signals from the mixers 36, 37 at outputs 38, 39 of the correctioncircuit 33 are connected to the respective record inputs 12, 11 of thetape recorder 10. The tape recorder playback outputs 14, 13 areconnected to inputs 310,311 of the correction circuit 33. The 5 kHzreference tones from the two channels are selected by band pass filters312,313 and are then connected to inputs to respective fluttercorrection circuits 314,315. One reference tone (316) is also connectedto a drift correction circuit 317 together with the 5 kHz output (120)from the oscillator 16 to provide a tape speed correction signal atoutput 318 of the correction circuit 33 for connection to the taperecorder motor speed control input 15. The 5 kHz output (120) from theoscillator 16 is also connected to respective inputs 319,320 of theflutter correction circuits 314,315 where phase comparison is made withthe 5 kHz output control signals. The two channel outputs 14,13 are alsoconnected directly to the respective inputs 321,322 of the fluttercorrection circuits 314,315. After phase correction the output signalsare filtered by 3 kHz low pass filters 323,324 and then connected torespective right and left channel outputs of the correction circuit 33.

The above arrangement applied to multi-channel recording enablesreduction of drift, wow and flutter in even unmeasureable levels. Inaddition, interchannel `skew` phase errors are automatically removed.Sound recordings made with this type of system will therefore reproduceexactly the spatial content of the original sound.

FIGS. 4-6 will now be referred to for a more complete description of thedrift correction. The drift correction circuit 317 (FIG. 3) determinesdrift by measuring the frequency of a control tone present in one ormore playback channels. This measurement is made against a stablefrequency reference. FIG. 4a shows a standard technique for frequencymeasurement. The control reference tone (316) after limiting (410) isused to step a binary counter 411 by one count for each cycle of theinput control tone. Every second a 1 Hz signal (412) causes the binarycount to be transferred to an output data latch store 413 and the binarycount is then reset and a new count started. Thus frequency measurementsare updated every second with a resolution of 1 in 5000 for a controltone of 5 kHz, i.e. an accuracy of ±0.01%. If a higher resolution isrequired the count period must be increased but the error of ±0.5 cyclewill remain the same. For drift measurement it is desirable to haveinfinite resolution, zero error and a very short measurement period.These are conflicing requirements when using the existing FIG. 4aarrangement. FIG. 4b shows a frequency measuring circuit which overcomesthis problem. The control tone (316) is connected to a cyclic binarycounter 414 which counts the input signal cycles without being reset.The count is latched to a data latch 415 at a much higher clock rate of50 Hz (414). The latch clocking frequency and the binary cycle countmust be a harmonic ratio of the control tone frequency (5 kHz). Thuswhere the counter 414 is Divide-by-100 as shown, the latch clockfrequency (416) must be 50 Hz or a multiple thereof. The output (417)from the data latch 415 will then automatically provide the frequencydifference count between the control tone (316) and the stable referencesource (16) used to produce the 50 Hz clock pulses (416). The resolutionis infinite and the counter error is zero and the update rate (50 Hz) isvery high.

FIG. 5 illustrates a use of the FIG. 4b cyclic frequency counter in adrift correction circuit 317. Filters (F) between the tape recorderoutput 13 and the input (316) to the cyclic counter 414 are not shownfor convenience. The 50 Hz clock pulses for the data latch 415 areproduced from the stable 5 kHz reference 16 by means of a divide-by-onehundred circuit 50. The 50 Hz signals representing the accumulatingbinary frequency errors (417) at the output of the data latch 415 isconverted by a digital-to-analogue converter 51 and an adjustableamplifier 52 into a control voltage signal 53 for connection to a speedcontrol input 15 of the tape capstan motor 54. The arrangement providesa negative feedback speed control loop such that if the speed of thecapstan motor 54, and hence the tape 55, is faster than it should be,the control tone frequency (316) from the playback amplifier 56 willincrease (i.e. 5 kHz+f, where f is the frequency increase). Thisincrease in frequency produces an increasing error count in the cycliccount circuit output 417 and thus a larger output from the D/A converter51. After appropriate amplification (52) and `sense` inversion thisoutput is used to reduce the speed of the motor 54. Conversely, if thespeed of the motor 54 is lower than it should be the control tonefrequency will decrease (5 kHz-f) and the feedback loop will thenincrease the speed until it is correct again. Thus the tape speed iscontinuously adjusted to maintain a zero frequency difference and aminimised count error between the reference source and the control tone,irrespective of the playback period. This means that there will be notime drift from the start of the recording to the end, relative toabsolute time. The maximum time shift error, after initialstabilisation, will normally be less than ±0.5 Hz, i.e. 0.0001 secs forany length of recording. This time error will be reduced to a very muchsmaller value by the wow and flutter correction (314, 315) to bedescribed in greater detail.

FIG. 6 shows the FIG. 5 drift correction circuit in greater detail. Thecontrol tone (13) from the tape recorder playback output is bandpassfiltered (60) to improve the signal to noise ratio, then limited (61) toremove any amplitude variations and then bandpass filtered to removeharmonics. The output signal S_(c) is then used as input (63) to thedrift correction circuit and as input (64) to each wow and fluttercorrection circuit. The function of this filtering and limiting is toremove, as far as possible, fading and dropouts in the control tonesignal T_(c). The input signal (63) to the drift correction circuit islimited once more (65) before connection to the binary counter 414. Thecycling of the counter 414 is determined by a detector 66 responsive tobinary 100 to produce a reset signal 67 for the counter. The 50 Hzcontrol tone samples from the D/A converter 51 are low pass filtered(68) and amplified (69) before connection to the feedback loop gainadjustment amplifier 52. The output signal from the amplifier 52 isconnected to the input of a light dependent resistor circuit 610, theoutput of which is connected to the tape motor speed control 15 of thetape recorder. An improvement to the drift correction performance can beobtained if the low pass filter 68 is replaced by a true voltageintegrator circuit 611 as also indicated in FIG. 6. As shown the output612 from the D A converter 51 is transmitted via a transconductor613/capacitor 614 integrator in place of the resistor 615/capacitor 616integrator in the low pass filter 68. Also shown in FIG. 6 a filter 617is connected to the output of the local oscillator 16 to provide asignal R_(s) for use as the recording control signal and for use in thephase correction circuits.

FIG. 7 shows a simple schematic negative feedback configurationincluding a phase detector 70 wherein the control tone S_(c) (71) andthe reference R_(s) (72) are compared. The control tone S_(c) (71)passes through a programmable analogue delay device 73 before connection(74) to the phase detector 70. The phase detector output V_(c) (75) hasa linear response 80 for phase differences between 0 and 2₁₁ as shown inFIG. 8. V_(c) is amplified (76) and then used to modulate a voltagecontrolled oscillator (VCO) 77. The VCO 77 provides a clock outputsignal 78 which varies the signal time delay through the analogue delaydevice 73. The feedback loop is arranged such that if the instantaneousphase, seen at the detector 70, advances (i.e. an increase in frequency)the VCO 77 frequency is reduced (by the amplified detector output) andthis produces an increased time delay through the analogue delay device73. Conversely reduced frequencies of S_(c) detected by the circuit areincreased by the delay device 73. The output S_(c) (79) will thus have areduced frequency deviation (wow and flutter).

The FIG. 7 circuit is used as shown in FIG. 9 to correct the analoguesignal output S_(s) (FIG. 1) from the tape recorder. The referencesignal R_(s) (72), and the drift connected control tone S_(c) (71)delayed by the analogue delay device 73 are both limited 90, 91 thenpassed through divide-by-two circuits 92,93 before phase differencedetection (70). The phase difference signal output 94 is low passfiltered (95) by a 6 dB per octave filter before amplification (76) andconnection to the VCO (77). The VCO clock output (96) is connected to asecond programmable analogue delay device 97, identical to the delay 73operating on the control tone S_(c). The second delay 97 is placed inthe path of the analogue signal output S_(s) (90) from the taperecorder. Before connection to the delay 97 the analogue signal S_(s) isamplified (99) and then filtered by a 10 kHz low pass filter 910. Thewow and flutter corrected output S_(s) ' (911) from the delay is firstfiltered by a 10 kHz low pass filter 912 and then amplified (913). Anoutput connection 914 carries the drift, wow and flutter corrected tonesignal S_(c) ' for measurement of residual fluctuation or for cascadedwow and flutter reduction processing. Since the circuit shown operatesto reduce measured wow and flutter in the control tone S_(c), it alsoreduces wow and flutter in the analogue recorded signal S_(s).

Since the corrected tone and analogue signals outputs S_(c) ' and S_(s)', 914 and 911, have the same wow and flutter, now at a greatly reducedlevel, the process of wow and flutter reduction can be repeated usingthe simplified cascaded circuit shown in FIG. 10 (with filters,amplifiers and limiters omitted for clarity). As can readily be seen thereference signal R_(s) (72), the corrected tone from the tape S_(c) '(914) and the corrected analogue recorded signal S_(s) ' (911) areconnected respectively to a second phase detector 100, a first delay 101and a second delay 102. The phase detector 100, delay 101 and a VCO 103are arranged in a second feedback loop 104 similar to the first feedbackloop 105. The further reduction in wow and flutter by this circuitresults in a double corrected output signal S_(s) " at the output 106 ofthe delay 102.

At a cost in circuit complexity the drift, wow and flutter correctioncircuitry may be made to operate on embedded control signals recorded ineach tape recorder channel. As mentioned earlier, this reducesinter-channel skew effects.

It can be shown that the wow and flutter component at the output of asingle correction stage will be reduced by a factor:

    1/(A/f.sub.m +1)

where A is the loop gain of the circuit and f_(m) is the wow and fluttervariation frequency. This is because the wow and flutter feedback loopcontains a simple 6 dB/octave filter which decreases the loop gaininversely proportional to the modulation frequency f_(m). The level ofcorrection will therefore be approximately inversely proportional to thefrequency of the wow and flutter variation. The above formula may beapplied to a typical measured recorded output where the modulation indexB=36, since;

    B=f.sub.c /f.sub.M,

where input frequency variation f_(c) =±54 and f_(m) =1.5 Hz.

Using a loop gain A of 73, the output modulation index B', aftercorrection, is given by: ##EQU1##

The deviation frequency f_(c) after correction is therefore ±1.1 Hz.

For a two stage cascaded correction circuit the overall reduction in wowand flutter is given by: ##EQU2##

In the above example, the output modulation index would be 0.015 and thefinal output deviation frequency would be ±0.02 Hz.

The figures given above have been found to agree with the measuredvalues.

FIG. 11 shows the anticipated performance of the correction system forsingle (111) and 2-stage (112) cascaded configurations over a range ofwow and flutter variation frequencies. The reduction figure in dBs isthe ratio change between the output modulation index (or frequencydeviation) to the input index (or deviation). From the previous example,for a 1.5 Hz wow signal the reduction is about 34 dB for a singlecorrection system, whilst for 10 Hz it is about 18 dB. These ratioswould be doubled for the 2-stage cascade circuit.

Referring again to FIG. 9, the 6 dB/octave low pass filter 95 introducessome undesirable phase delay/distortion and a limited loop gain of 73was selected to minimise the risk of circuit instability. Byimplementing the circuit principles shown with established digitalprocessing techniques a higher loop gain can be achieved without theassociated fall off in frequency. These circuits would be made morestable, more reliable, and with enhanced performance. In addition thetape motor speed control would be improved by digital implementation.Such digital implementation will be apparent to those skilled in thisart and circuit details are therefore not given.

The drift, wow and flutter correction system described can be used todramatically improve the phase, frequency and time keeping (drift)characteristics of any recording process. The accuracy and stability ofthe correction process depends entirely upon the stability of thereference tone being used during recording and playback. The amount ofwow and flutter correction will depend upon the wow and flutterfrequency of variation and the loop gain value of the system, `A`.Generally, the lower the wow and flutter variation frequency, then thebetter the correction will be, as shown in FIG. 11. Cascaded systems canbe used to provide even better correction characteristics but care mustbe taken to ensure that the dynamic range is not reduced by spurioussignals produced within the analogue delay devices. This however can beavoided if digital techniques are used for analogue delay lines.

FIGS. 12 and 13 show single and 2-stage digital delay lines 120, 130which can replace the analogue delay devices shown in the previouscircuits. In both arrangements the audio input signal 121 is sampled at40 kc/s by a 16-bit A/D converter 122 and the 16-bit output from thedigital delay is reconverted to an analogue audio signal by a D/Aconverter 123. The single correction stage includes a single digital`First in First out` (FIFO) delay 120 controlled by a delay clock signal(124). The 2-stage correction circuit includes series connected FIFOdelays 131 and 132 controlled by first and second delay clock signals(133 and 134).

This control technique can not only be used to upgrade the quality ofexisting `professional` instrument tape recorders but it can also beused to transform the performance of what would normally be unacceptablevery poor systems, such as compact (personal) tape recorders. This hasvery important applications where the cost of producing a consumableminiature, robust, high quality recorder would otherwise be prohibitive.

Although specifically designed for recording systems the techniquedescribed herein can also have applications in other areas where thesignal `propagating` medium has a delay which is time variant but whichis otherwise non time dispersive.

The invention requires correction of the drift before phase correctionscan be applied, and in the arrangements described drift is corrected bycontrol of the tape capstan drive motor. This control may be direct orfor convenience it could be via a light sensitive resistor circuit asshown, depending upon the tape recorder being used. In some taperecorders drift may not be a serious problem and also it may bedesirable to control wow and flutter without controlling the capstandrive motor. FIG. 14 shows a possible alternative arrangement for theinvention for these cases. The reference signal at output 140 includescomponents of drift, wow and flutter. Instead of correcting thisreference signal for drift, this circuit arrangement imposes a similardrift on the local oscillator reference signal to enable a phasecomparator circuit to correct for wow and flutter. The output 140 isconnected to a counter circuit 141, as in FIG. 6, with an outputconnected to a D/A converter 142 by latch control signals from adivide-by-hundred circuit 143. The output from the D/A converter 142, isconnected via a low pass filter 144 and amplifier 145 to a control inputof a 5 kHz reference oscillator 146. The arrangement is such that thefrequency of the oscillator output 147 is locked to the mean frequencyof the reference signal at the output 140 of the tape recorder. Insimilar manner to the previous examples this local reference signaloutput 147 and the recorded reference output 140 are connected to aphase comparator circuit 148 by means of which (149, 1410) a delayelement in the signal output 1411 from the tape recorder is adjusted tocompensate for wow and flutter variations. As before this approach maybe applied to embeded recorded reference signals and cascaded phasecorrection circuits may be used.

In the arrangements thus far described, the output from thetape-recorder has random phase variations superimposed on the signalafter correction by the tape speed controller. Correct operation of thephase error correction circuits described requires that the phasevariations at the input to the delay lines used are uncorrelated withthe output. This is ensured by making the delay long enough. Thecircuits work by comparing the phase of the delay output with the phaseof a reference signal. If the output phase lags then the clocking rateof the delay is speeded up for correction and visa versa. At the input,however, the effect of speeding up the clock rate of the delay is toincrease the rate of sampling of the signal from the tape-recorder andthus to slow down the sampled signal in the delay. As these samples workthrough to the output of the delay a further speeding up of clock rateoccurs. If the length of the delay is long enough such that input andoutput are uncorrelated then this phenomenon is not harmful, however,where there is correlation there could be an uncontrolled rise in theclock rate. A further disadvantage of the described arrangements arisesfrom the use of a low pass filter in converting the output from thephase comparator to a voltage signal for varying the frequency of avoltage controlled oscillator. This arrangement does not work quicklyand so the correction falls with increasing frequency.

A modification of the tape recorder circuits, with tape speed correctedfor the sake of clarity, is illustrated in FIGS. 15 and 16 using digitalciruitry. The speed control and detailed circuit arrangement are shownin FIG. 17. A control signal 151 from the tape-recorder 152 isdigititally sampled by an analogue to digital converter 153. The outputof the A/D converter 153 is connected to a variable delay shift register154 implemented in random access memory (RAM). Control signal samplesare read out by a programmable tap connection 155 shown centrallypositioned along the delay 154, the tap position therefore determiningthe sample delay. The digital samples are then connected via an outputsignal latch 179₁ to a digital to analogue converter (D/A) 156, filtered(157), then connected to one input of a comparator circuit 158. A clockreference signal 159, having the same frequency as the recorded controlsignal, is connected to a second input of the comparator 158. Thecomparator measures the time differences between successive cycles ofreference and control signals. These time differences are added to theread address (155) to the delay 154. By this means the read position ofthe delay RAM is advanced or retarded with respect to the write addressdepending on whether the time difference is positive or negative and thedelay is varied to reduce the time difference measured by the comparator158 to zero. The signal output 1510 from the tape-recorder 152 isconnected in similar manner via A/D converter 1511, RAM delay 1512, RAMread out 1513 via signal latch 179₂ to D/A converter 1514, and filter1515 to the output 1516. The read out address (1513) of delay 1512 iscontrolled in the same way as the read out from the control signal delay154 by the output from the comparator 158. Operation of the RAM outputlatches 179₁ and 179₂ will be described below with reference to FIG. 17.In this arrangement the control signal 151 and the signal 1510 from thetape-recorder may, for economy, be digitised with different resolutionA/D conversions. For example a much higher resolution (14 bits) may beadopted for the signal channel to retain signal fidelity, whereas thecontrol signal can use a much lower resolution of 8 bits (say).

The operation of the comparator 158 can be appreciated more easily byreference to FIG. 16. The reference and control signals S₁ and S₂ to becompared are limited to produce square waves and the leading edges 161,162 are used respectively to clock and read a 1 MHz counter whichenables the time difference Δt to be measured to an accuracy of ±1/2μsec. In one particular arrangement using a 5 kc/s control signal, a 2kbit RAM delay 154 is used and the signal is sampled at a rate of 50kc/s; i.e. the delay 154 is clocked at this rate. Thus about 200 cyclesof the control signal are stored in the delay 154. Changing the tap 155by one position is then equivalent to a delay change of 20 μsec. Thetime difference Δt is determined in the form (N×20+n) μsec where N and nare integers and n is in the range 0 to 19 μsec. N is then the numbercorresponding to the change of address of the tap 155, positive ornegative, and n is a fine adjustment delay applied to the output signallatches 179₁ and 179₂.

As shown in FIG. 17 the tape motor speed control 171 is effected byconnecting the control signal output 151 from the tape recorder to the"count down" input of an up/down counter 172 and a 50 kHz referencesignal from the clock 159 is connected to the "count up" input. Thedigital count output from the up/down counter 172, representing the timedifference (control cycles) between the control signal from the taperecorder and the reference signal, is connected to a digital to analogueconverter 173. The analogue output from the D/A converter 173 is thenconnected to the tape recorder to control the playback tape speed insimilar manner to the FIG. 5 arrangement.

The drift corrected control signal after transmission through theprogrammable RAM delay 154 is connected to the Δt measuring circuit 158where the phase time difference from the reference signal from clock 159is measured. The time difference is recorded by two counters: Counter174, clocked by a 5 kHz signal giving the number N of 20 μsec intervalsand a second counter 177, clocked by the 50 kHz reference signal, givingthe number n corresponding to microseconds in the range 0-19 μsec. Thenumber N in the binary counter 174 shall be arranged to count thereference clock (derived from 159) such that the count number will runfrom -5 (minus 5) through zero to +5 (plus 5) then reset to -5 andrepeat thereafter. In this manner the time difference Δt in 158 willnormally be zero but will read positive (0 to +5) for an increase intime delay of control signal, S₂, and will record a negative number (0to -5) for an advanced time delay of control signal S₂, relative toreference signal S₁. In this fashion the RAM address, 155, will beeither advanced or retarded in time if the signal is retarded oradvanced respectively and will therefore have all time delays (to 1 μsecaccuracy) removed. The corrected signal will therefore always be within±1 μsec of time (referred to reference) and the maximum wow and fluttertime distortion will also be with ±1 μsec and this will be irrespectiveof the taperecorder wow and flutter deviation or rate of deviation(modulation frequency). The number n is connected to a clock phase latchadjusting circuit 178. The phase adjuster 178 provides a clock latchingoutput signal C_(L), dependent on n, to control the phase delay of theclock 159 which is used to operate a one sample (8 bits wide) latch 179.Since the phase of the control signal may be advanced or retarded incomparison with the reference signal, the value of N (the number of 20μsec intervals by which the RAM delay address 155 is changed) must beadjusted to ensure that n always represents a phase delay. This isachieved by adding to N in an adder 175 a binary 1 whenever the desiredphase change C_(c) for latch 179 is greater than the existing latchphase delay C--C_(L). This "change of address" output from adder 175 isthen added to the current RAM tap Read address (held in latch 176) in afurther adder 1710. The output from this adder is then stored in latch176 fusing a delayed (157') version of the control tone from filter157--to allow for signal propagation delays through address 175 and1710] and provides the new address for the tap 155. At start-up, the RAMaddress latch 176 has an address corresponding to the centre address ofthe RAM 154.

As described, the n counter 177 and the binary (-5 to 5) counter 174 arearranged such that the remainder n always represents a delay forretarding the 50 kHz clock 159 used to clock signal samples from thedelay 154. Thus if Δt=-50 μs, representing the time needed to retard (intime) the control signal, then N is set at -2 and n at 10 μs. Thus theread address is delayed by two additional places away from the RAM writeaddress (FIG. 15), representing an increase in RAM delay of 40 μs, andthe output latch clock pulses are delayed by n=10 μs. Where a timeadvance Δt=45 μs (say) is required, the circuitry is arranged such thatthe binary counter N is increased by 3, i.e. binary 3 is added to theread address and the read tap is moved three places closer (earlier) tothe RAM write address (FIG. 15) corresponding to an advance of 60 μs.The remainder n is then provided as a delay of 15 μs to the output latch(179) clock C_(L) whereby the resulting advance is 45 μs. The outputlatch 179 thus provides a means by which the signal output can be timecorrected in 1 μsec intervals. Without this latching technique thesignals could only be corrected in 1 μsec intervals (signal samplingrate) by altering the read address. to achieve this accuracy otherwisewould require a 1 MHz clock RAM, 40 kbits long, and an A/D converteroperating at 1 MHz. This is neither practicable nor affordable.

As in the arrangements described previously the comparator 158 isarranged to provide signals for simultaneous adjustment of the phaseoutput latch 179₂ clock C_(L) and the read address for the signal delay1512. The output signals from the delays 154 and 1512 after conversionto analogue form are passed through anti-sampling filters 157 and 1515respectively to filter out the sampling frequencies (50 kHz). The filter157 must have an impulse response of less than 200 μsecs for otherwisethe phase/time corrections made to the control signals will not havepropagated through the RAM (154), latch (179), filter (157) andcomparator (158) by the time (200 μsec later) the next correction is tobe made. If this should happen the `system` may "recorrect" the sameprevious time errors. This could then lead to either instability or asustained "ringing" effect in the correction circuit and therefore onthe signals.

In alternative arrangements the circuitry could be arranged such that anadjustment is first made and thereafter at 400 μs intervals (ormultiples of 200 μsec where the control tone is 5 KHz giving a period of200 μsec) rather than every 200 μs. By this means the impulse response(ringing time) delay of the filter 157 may be allowed to be greaterwithout causing instability.

I claim:
 1. A signal correction system for correcting playback of asignal, said system including:a recording system, said recording systemincluding a means for recording said signal and a control referencetone; and a playback receiving means for playing back said recordedsignal and said recorded referenced tone, wherein said receiving meansincludes:a local oscillator means for generating an identical tone tosaid control reference tone; frequency comparator means for comparing afrequency of said recorded reference tone with a frequency of said localoscillator means tone, said comparator means including a continuouslycounting cyclic counter for providing an output indicative of anyaccumulated difference in frequency of said recorded reference tone andfrequency of said local oscillator means tone; drift correction means,responsive to the comparator means, for applying a common frequencyshift to the played back signal and said played back control referencetone, and for reducing to zero any difference output from the comparatormeans and for providing a drift-corrected signal and a drift-correctedcontrol reference tone; a phase comparator circuit for comparing phaseof said drift-corrected reference tone with phase of the localoscillator means tone and for providing an output indicative of anyphase difference between said drift-corrected reference tone and saidlocal oscillator means tone; and short term fluctuation correctionmeans, responsive to said phase comparator circuit output, for applyingto said played back signal and the drift-corrected reference tone, acommon phase delay to reduce to zero any difference output from saidphase comparator circuit, thereby providing a drift-corrected and phasecorrected played back signal.
 2. A signal correction system forcorrecting transmission of a signal, said system including:atransmission system, said transmission system including a means fortransmitting said signal and a control reference tone; and a receivingmeans for receiving said transmitted signal and said transmittedreferenced tone, wherein said receiving means includes:a localoscillator means for generating an identical tone to said controlreference tone; frequency comparator means for comparing a frequency ofsaid received control reference tone with a frequency of said localoscillator means tone, said comparator means including a continuouslycounting cyclic counter for providing an output indicative of anyaccumulated difference in frequency of said received control referencetone and frequency of said local oscillator means tone; drift correctionmeans, responsive to the comparator means, for applying a commonfrequency shift to the received signal and said received controlreference tone, and for reducing to zero any difference output from thecomparator means and for providing a drift-corrected received signal anda drift-corrected control reference tone; a phase comparator circuitmeans for comparing a phase of said drift-corrected control referencetone with a phase of the local oscillator means tone and for providingan output indicative of any phase difference between saiddrift-corrected control reference tone and said local oscillator meanstone; and short term fluctuation correction means, responsive to saidphase comparator circuit output, for applying to said drift-correctedreceived signal and the drift-corrected reference tone, a common phasedelay to reduce to zero any difference output from said phase comparatorcircuit, thereby providing a drift-corrected and phase correctedreceived signal.
 3. A signal correction system as claimed in claim 1 or2, wherein said cyclic counter comprises a cyclic binary counter havingan output said cyclic binary counter is clocked by a signal derived fromthe local oscillator means.
 4. A signal correction system as claimed inclaim 3 further including a detector, wherein cycling of the binarycounter is determined by said detector connected to said binary counterand responsive to a predetermined binary number (N_(p)) to provide areset signal to the binary counter.
 5. A signal correction system asclaimed in claim 4 wherein a binary counter is produced by connecting anoutput from the local oscillator means to the input of adivide-by-N_(p/n) divider, where n is an integer.
 6. A signal correctionsystem as claimed in claim 5 wherein the output from the binary counteris clocked into an output latch circuit and a latch output is connectedto a D/A converter said latch circuit and said D/A converter comprisinga means for producing analogue signal samples representative of thefrequency time drift between the control reference tone and the localoscillator means tone.
 7. A signal correction system as claimed in claim6, further including an active voltage integrator circuit, wherein saidanalogue signal samples are connected to said active voltage integratorcircuit, said integrator circuit comprising a transconductor and acapacitor.
 8. A signal correction system as claimed in claim 6 theanalogue signal samples are connected to said local oscillator means andcomprise a means for changing the frequency of oscillation of said localoscillation means.
 9. A signal correction system as claimed in claim 1or 2 further including bandpass filter and limiting means for minimizingthe effects of fading and dropouts on said control reference tone.
 10. Asignal correction system as claimed in claim 1, wherein the frequencycomparator means comprises an up/down counter having a count down inputand a count up input, the played back control reference tone and thelocal oscillator means tone are connected to respective count down andcount up inputs, and an output difference signal is connected to a meansfor reducing to zero the frequency difference between the played backcontrol reference tone and the local oscillator means tone.
 11. A signalcorrection system as claimed in claim 10, further including a digitaltime delay circuit and an A/D convertor for connecting said played backsignal to a digital signal, wherein said common phase delay is appliedby said digital time delay circuit, said time delay circuit comprising aprogrammable RAM delay, a series connected RAM latch, and a phaseadjuster for the latch, where said digital signal is clocked in to aWrite address of the RAM delay at frequency F and is read out from aprogrammable Read Address of said RAM delay to the latch to provide atime delay having incremental value ΔT of 1/F, a clock signal to the RAMlatch is delayed by a digitised time having an incremental value Δt inthe range 0 to 1/F, to thereby provide an overall time delay to anaccuracy of Δt.
 12. A signal correction system as claimed in claim 11wherein said phase comparator comprises:limiter means for squaring thedrift corrected control tone and the local oscillator control referencetone; and a counter responsive to the leading edges said squared toneand signal so as to be triggered by the local oscillator controlreference tone and read by the played back drift corrected tone.
 13. Asignal correction system as claimed in claim 12 wherein said counter hasa clock frequency which is n times the frequency F and the phasecomparator circuit measures the phase difference in units of N+R wherethe units of N are 1/F and the units of R are 1/nF.
 14. A signalcorrection system as claimed in claim 13 further including means formodifying said phase difference N+R, which may be positive or negative,by a conditional change of N such that R always represents a delayedphase difference.
 15. A signal correction system as claimed in claim 14further including an adder, wherein a Read address for the RAM is storedin a Read latch connected to said adder such that it can be adjusted bysaid modified N and R to set the delay for the RAM latch.
 16. A signalcorrection system as claimed in claim 1 for reduction of drift, wow andflutter in a tape recorder, said tape recorder including at least onerecord head, wherein said local oscillator means comprises a singlestable reference oscillator connected to the tape recorder such that,during recording, said control reference tone is applied to said atleast one record head of said tape recorder with the frequencycomparator means and phase comparator circuit disabled, and, onplayback, the recorded signals to be corrected, together with the playedback control reference tone, are connected to the local oscillatormeans, frequency comparator means, drift correction means, phasecomparing circuit and short term fluctuation correction means.
 17. Asignal correction system as claimed in claim 16 wherein said taperecorder is a multichannel tape recorder and said control reference toneis provided as a reference embedded in each input channel of saidmulti-channel tape recorder.
 18. A signal correction system as claimedin claim 16, wherein the control reference tone is provided as areference in a dedicated reference channel.
 19. A signal correctionsystem as claimed in claim 17 or 18 wherein said tape recorder includesa tape capstan motor drive and the drift correction means includes adrive signal connected from the output of the frequency comparator meansto the tape capstan motor drive for varying the capstan motor drivespeed.
 20. A signal correction system as claimed in claim 19 wherein alight dependent resistor is used to correctly interface between thefrequency comparator and the tape capstan motor drive.
 21. A signalcorrection system as claimed in claim 1, wherein said correction meanscomprises a fast programmable delay circuit and a voltage controlledoscillator (VCO), a voltage output from the phase comparator (70) isconnected to an input of the VCO and a VCO output is connected to thedelay circuit to minimize said phase comparator circuit phase differenceoutput.
 22. A signal correction system as claimed in claim 21 furtherincluding limiters connected to the inputs of the phase comparatorcircuit.
 23. A signal correction system as claimed in claim 21 furtherincluding a second fast programmable delay circuit, wherein the outputsignal from the VCO is connected to said second delay circuit, identicalto said first delay circuit: the drift corrected signal being connectedto an input to the second delay circuit and a drift and short termfluctuation corrected signal provided at an output of said second delaycircuit.
 24. A signal correction system as claimed in claim 23 furtherincluding low pass filters connected at the input and output of thesecond fast programmable delay circuit.
 25. A signal correction systemas claimed in claim 23 wherein each delay circuit is a digital delaycircuit.
 26. A signal correction system as claimed in claim 25, whereina plurality of phase comparator circuits are provided.
 27. A signalcorrection system as claimed in claim 21, further including a 6dB/octave low pass filter connected between the phase comparator meansand the VCO.